Certain embodiments of the present invention provide an approach to perform adaptive run-time CPU power management in a system employing a central processing unit (CPU) and an operating system. In particular, certain embodiments provide for monitoring actual processes of the CPU from one time segment to another and adjusting the throttling of the CPU for the next time segment.
A CPU is the computing and control hardware element of a computer-based system. In a personal computer, for example, the CPU is usually an integrated part of a single, extremely powerful microprocessor. An operating system is the software responsible for allocating system resources including memory, processor time, disk space, and peripheral devices such as printers, modems, and monitors. All applications use the operating system to gain access to the resources needed. The operating system is the first program loaded into the computer as it boots up, and it remains in memory throughout the computing session.
Advanced CPUs are achieving higher performance as time goes on but, at the same time, are consuming more power and generating more heat making systems the use the CPUs more difficult to be implemented, especially in mobile form factors such as notebook computers, hand-held PDAs, or tablet PCs. Even for desktop PC implementation, the heat generated by the advanced CPUs mandates an active cooling mechanism, such as a fan sink, creating undesirable acoustic noise.
Previously, CPU power management has been implemented using an external power management controller (PMC) to monitor system activities at known legacy I/O or memory addresses to determine power management policy for an individual device. If all relevant system resources are powered down, then the PMC may then put the CPU into a lower power state.
For the Microsoft Windows® operating system environment, some software schemes use a so-called “CPU Cooler Program” to execute a halt instruction, or a “Ring 0 Program” to put the CPU into a lower power state when the operating system or applications are idle. The program takes advantage of the fact that the operating system will execute the “idle loop software module” when Windows® is not busy. The approach is only effective, however, if all tasks are idle and reported to Windows® as such.
More recently, Microsoft et al. published the ACPI (Advanced Configuration Power Interface) power management specification that is intended to provide a standardized, operating system-independent and platform-independent power management mechanism to enable the OSPM (operating system-directed power management) initiative. An ACPI-compatible operating system may balance CPU performance versus power consumption and thermal states by manipulating the processor performance controls.
OSPM is very effective for peripheral device power management, such as for UARTs or modems, since OSPM knows whether the port is opened or the modem is in use. However, OSPM is not effective with CPU power management since OSPM does not know nor can it predict the CPU workload. Therefore, OSPM is not able to set the CPU to the appropriate power state to execute user tasks without performance degradation while minimizing power consumption.
The ACPI specification defines a working state in which the processor executes instructions. Processor sleeping states, labeled C1 through C3, are also defined. In the sleeping states, the processor executes no instructions, thereby reducing power consumption and, possibly, operating temperatures.
Typically, the operating system puts the CPU into low power states (C1, C2, and C3) when the operating system is idle. In the low power states, the CPU does not run any instructions and wakes when an interrupt, such as the operating system scheduler's timer interrupt, occurs. Each processor sleeping state has a latency associated with entering and exiting that corresponds to the power savings. In general, the longer the entry/exit latency, the greater the power savings when in the state.
The C1 power state has the lowest latency. The hardware latency must be low enough such that the operating software does not consider the latency aspect of the state when deciding whether or not to use it. Aside from putting the processor in a non-executing power state, there are no other software-visible effects.
The C2 state offers improved power savings over the C1 state. The worst-case hardware latency is provided by way of the ACPI system firmware and the operating software may use the information to determine when the C1 state should be used instead of the C2 state. Aside from putting the processor in a non-executing power state, there are no other software-visible effects.
The C3 state offers improved power savings over the C1 and C2 states. The worst-case hardware latency is provided by way of the ACPI system firmware and the operating software may use the information to determine when the C2 state should be used instead of the C3 state. While in the C3 state, the processor's caches maintain state but ignore any snoops. The operating software is responsible for ensuring that the caches maintain coherency.
The operating system determines how much time is being spent in its idle loop by reading the ACPI Power Management Timer. The timer runs at a known, fixed frequency and allows the operating system to precisely determine idle time. The operating system will put the CPU into different quality low power states (that vary in power and latency) when it enters its idle loop, depending on the idle time estimate.
Whenever the operating system enters its idle loop and the processor is put in a low power state, an external event is typically relied upon to wake up the processor. The external event may be, for example, a keyboard stroke or a timer tick. Current operating systems use the timer tick to wake up the CPU regularly. When the CPU wakes up, it gets out of the idle loop and checks to see if there are any other task requests. If not, the CPU may enter its idle loop again and go to a low power state.
The operating system keeps track of the percentage of time that the CPU is idle and writes the idle percentage value to a register. For example, the CPU may have been idle for about 40% of a last predefined time period. Different operating systems use different windows of time to compute the idle percentage value. Older operating systems have longer idle loops. Newer operating systems have shorter idle loops in order to accommodate as many tasks as possible running simultaneously.
While in the working state (not sleeping), ACPI allows the performance of the processor to be altered through a defined “throttling” process and through transitions into multiple performance states.
Other CPU power management schemes are also known which use statistical methods to monitor CPU host interface (sometimes known as Front-Side Bus) activities to determine average CPU percent utilization and set the CPU throttling accordingly. However, advanced CPUs incorporate large caches which hide greater than 90% of the CPU activities within the CPU core. Therefore, the FSB percent utilization has little correlation to the actual core CPU percent utilization. As a result, prior implementations cannot correctly predict CPUs with super-pipelined architectures and integrated caches.
Cache is a section of very fast memory (often static RAM) reserved for the temporary storage of the data or instructions likely to be needed next by the processor.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with embodiments of the present invention as set forth in the remainder of the present application with reference to the drawings.
These and other advantages, aspects and novel features of the present invention, as well as details of an illustrated embodiment thereof, will be more fully understood from the following description and drawings.